The present invention relates to information processing systems including processing devices having cache memories and coupled to a shared main storage memory, and more particularly to a means for ensuring the integrity of data in the cache memories while increasing the speed of fetch and store accesses to the cache memories and main storage.
In information processing networks with multiple processing devices sharing a common main storage memory, cache memories can substantially enhance network performance. A plurality of cache memories can be provided, one within and uniquely associated with each of the processing devices and containing some of the information stored in the main memory. Whenever one of the processing devices performs data store or fetch operations in its associated cache memory rather than in the shared main memory, memory access time is substantially reduced. Generally there are two types of cache memories: store-through cache memory in which data is provided to the shared main memory each time it is stored in one of the cache memories; and store-in-buffer cache memory, in which the immediate store is just to the cache memory. The store-in-buffer cache memory handles all stores of its associated processing device, and thus requires fewer accesses to shared main memory, for a reduced main storage bandwidth. At the same time, store-in-buffer cache memories require more intercommunication circuitry among the cache memories and main storage, to ensure that main storage is kept current with the most recent update to any of the cache memories.
U.S. Pat. No. 4,484,267 (Fletcher) discloses an attempt to gain the advantages of both types of cache memory, namely a hybrid cache control selectively combining certain features found in store-in-buffer cache memories and store-through cache memories. The cache control utilizes a sharing flag associated with each line representation in each cache directory in a multiple processing device system. The flag uniquely indicates, for each line, whether the line is to be handled as a store-in-buffer line or a store-through line. The hybrid control reduces the required main storage bandwidth as compared to a similar network using store-through cache memories, since the control is only occasionally required to send stores to the main storage memory. On the other hand, as compared to a system employing store-in-buffer cache memories, the hybrid system improves performance.
Another approach to improving network performance is disclosed in U.S. Pat. No. 4,695,951 (Hooker et al), directed to a system of multiple processing devices, each having a store-into type cache memory. Data modified by a processor is stored in its associated cache memory. When another processor requires data from the same location, the data may be transferred directly from the original processor to the requesting processor, rather than to the requesting processor through main storage.
U.S. Pat. No. 4,439,829 (Tsiang) discloses a network in which a cache memory cycle is divided into two parts: a first part dedicated to processing device read requests, and a second part directed to all other operations, including fetching an address from a processor to check its associated cache memory, and writing to the cache memory. This division is said to eliminate certain contentions and the need to resolve them, and thus improve processing speed.
Any cache memory includes a table of main storage memory locations or addresses. Such table specifies not only the main storage locations which have been mapped into the cache memory, but also whether each particular location is valid or invalid. This table, herein referred to as a cache directory, further may hold certain status bits associated with the cache memory locations and their associated main storage memory locations.
For example, in certain information processing systems it is desired to identify some of the data words as "pointers" which contain, along with other data bits, an address identifying a particular byte or number of bytes within main storage memory. Pointers are distinguished from other data words by hardware tag bits which, when set, identify their associated data word as a pointer. Tag bits can be set only by tag instructions, with all other instructions resetting the tag bits. Accordingly, if a pointer is inadvertently modified by a data handling instruction rather than a tag instruction, the reset tag bits identify the pointer as no longer valid.
To enhance system performance, it is advantageous to store pointers and other data words mixed, i.e. without the need to reserve particular areas in main storage for exclusive use of pointers. Further, however, an information processing network might include devices utilizing formats which do not allow tag bits within data words. This creates the need to modify the tag bits in data words transmitted between main storage memory and such devices. To this end, when data words are moved from main storage memory to the devices, the tag bits are extracted, i.e. accumulated and saved in a separate field, e.g. in the cache directory of a processing device. In this type of network, the cache directory not only specifies the main storage locations mapped into the cache memory and their validity, but also holds status bits associated with such locations, for identifying the data at the location as an address pointer or in some other manner signifying the status of the data.
In connection with store-through cache memories, data storage operations are performed in two steps or clock cycles. During the first cycle, the cache directory is read to determine whether: (1) the target (requested) main storage memory location is currently mapped into the cache memory; (2) the target main memory location is currently mapped, and the status bits require update; or (3) the target main memory location is not currently mapped into the cache memory. An action during the second cycle is based on the results of the read. If the target main storage memory location was previously mapped into the cache memory, the store is completed and, if necessary, status bits are updated. If the target main storage memory location was not mapped into the cache memory, either the cache memory is bypassed and the data stored only in the main storage memory, or a line equivalent to the main storage location is fetched for the cache memory before the store operation is completed. In any event, each data storage operation requires at least two clock cycles.
Ideally, a cache memory would allow a data access (i.e. a store or fetch operation) every clock cycle, which of course would double the speed of such operations, given the same clock cycle. The "overhead" involved in providing separate cycles for checking the cache directory and for the actual store has been considered necessary to ensure the integrity of data stored in the cache memory.
Therefore, it is an object of the present invention to provide a data processing network including at least one processing device having a store-through cache memory, in which the speed of store and fetch operations is substantially increased at no loss of data integrity.
Another object of the invention is to provide a system in which a store of data to a store-through cache memory, and a compare or read of the cache directory, occur during the same clock cycle.
A further object is to provide a system of multiple processing devices sharing a main storage memory, with each of the processing devices including a store-through cache memory, with virtually no overhead associated with reading the cache directories.
Yet another object is to provide a process for storing to a store-through cache memory and to main storage once each clock cycle unless a different main storage location is resident and marked valid in the cache memory, and further for interrupting the associated processing device to identify a cache line as invalid in the event that a different main storage location is resident in the cache memory.